1. Field of the Invention
The present invention relates to a method for manufacturing nonvolatile semiconductor memory device which is equipped with floating gate.
2. Description of the Related Art
A nonvolatile semiconductor memory equipped with a floating gate is known well as EPROM etc. This kind of memory device comprises a big floating gate array arranged like lattice work on a semiconductor chip.
To begin with, a conventional method for manufacturing this kind of device will be described, referring to FIG. 2. Each process which comprises the method of conventional art is shown in FIG. 2(a) to FIG. 2(e).
As shown in FIG. 2(a), in an initial process of manufacturing memory device, on a silicon substrate 1, a field oxide film 2 is formed by LOCOS method which is known in public. This field oxide film 2 is formed like latticework. In FIG. 2(a) to FIG. 2(e), shown is a section of a portion of silicon substrate 1 located between neighboring lattices. Thus, the surface of silicon substrate 1 is divided into blocks, so as to form regions for memory elements.
In FIG. 2(b), a gate oxide film 3 is generated by oxidation with heat-treatment. This comprises an insulating film for insulating a floating gate from the silicon substrate 1.
And, on this gate oxide film 3, generated is a first poly-silicon 4, which includes N-type impurity, by LPCVD method known in public. This comprises a portion of a floating gate in the later process.
Here, for the purpose of finishing a floating gate adequately, when it is formed in the later process, the first poly-silicon 4 is treated as follows.
That is, a lattice patterning is performed by photo-lithographic etching technique known in public. And, formed is each first poly-silicon 4 divided into each element.
In FIG. 2(c), at first, an IPO film 5, which comprises ONO film etc. is generated by a certain method known in public. This is an intermediate insulating film between the floating gate and a control gate. As an example of this, a three-storied structure of oxide film, nitride film and oxide film, is used.
After this, a second poly-silicon 6 which includes N-type impurity, is generated by LPCVD method known in public. This is going to comprise a portion of control gate in the later process.
Next, a high melting point metallic suicide 7 such as WSix etc. is formed by spattering method or LPCVD method known in public. This is going to comprise a portion of control gate in the later process.
In FIG. 2(d), patterning is performed by photo-lithographic etching technique known in public. By this patterning, formed is a control gate 8 which comprises high melting point metallic silicide 7 and second poly-silicon 6. In addition, formed is a floating gate 9 which comprises first poly-silicon 4. These are performed by etching suicide 7, second poly-silicon 6, IPO film 5, first poly-silicon 4 and gate oxide film 3 respectively in this order. In this occasion, suitable dry-etching method is used for each etching
In FIG. 2(e), at first, masking oxide film 11 is generated by heat oxidation. After this, N-type impurity is implanted into the source and drain regions by photo-lithographic implantation technique known in public. And, an N+ impurity diffusing region 12 is formed by annealing. Thus, the source and drain regions of memory element are formed.
However, the conventional art mentioned above has some problems as follows.
In FIG. 2(b), as a result of patterning the first poly-silicon 4, there is a region where the first poly-silicon 4 is already removed from the silicon substrate. This is a region of boundary portion between the patterned poly-silicon 4.
In FIG. 2(d), an over-etching occurs at the region of this boundary portion, when the first poly-silicon 4 is etched. As a result, a region 10 where the portion of silicon substrate 1 is gouged away, is generated.
Therefore, in FIG. 2(e), at the step portions of both sides of the region 10, the density of impurity (N+) about horizontal direction in the drawings, locally decrease, causing high resistant region 13.
By such a high resistant region 13, source line resistance increases. As a result, caused is an inconvenience of deteriorating writing characteristic of memory cell.
To relieve this inconvenience, what is easily conceived is to adopt a simple method of increasing the density of N+ impurity which is implanted into source and drain regions, not to cause regions where N+ impurity density becomes thin. Moreover, other methods can be conceived. Those are a method of increasing annealing temperature or a method of extending annealing time, so as to form N+ impurity diffusing region deeply. But, these methods have a side effect. That is, by these methods caused is another inconvenience of increasing effect of shortening channel between source and drain. So, these methods are not practical.
Therefore, there had been a subject of relieving these inconveniences adequately.
Meanwhile, there is a conventional method of diffusing impurity selectively into the step portions of region 10 (c.f. JP 03-211774).
However, this method needs an etching technique of RIE method, to form impurity portions at the side wall of the step portions. So, this method comprises rather complicated process.
The present invention adopts the following configuration to solve the problems mentioned above.
As a first configuration, provided is a method for manufacturing nonvolatile semiconductor memory including the following processes.
As a first process, a first poly-silicon is patterned to divide the first poly-silicon into each memory element and expose silicon substrate portions which comprise boundary of the memory element.
As a second process, a second poly-silicon is formed on silicon substrate which boundary portions are exposed by patterning the first poly-silicon.
As a third process, a first impurity diffusing region is formed by diffusing impurity, which is included in the second poly-silicon, into the silicon substrate portion at the first poly-silicon boundary, with heat-treatment.
As a fourth process, a control gate and a floating gate is formed by using the first poly-silicon and the second poly-silicon as a material of a floating gate, forming a material of an intermediate insulating film on this material, forming a material of a control gate on this material, and etching these materials.
As a fifth process, a second impurity diffusing region, which includes source and drain regions of a memory element, is formed in the silicon substrate, and this second impurity diffusing region is connected with said first impurity diffusing region.
Moreover, forming a first impurity diffusing region is performed by the heat-treatment of forming a material of an intermediate insulating film.
As a second configuration, provided is a method for manufacturing nonvolatile semiconductor memory including the following processes.
As a first process, a first poly-silicon is patterned to divide the first poly-silicon into each memory element by local oxidation of silicon and form a first oxide film at the boundary portions between the memory element.
As a second process, a control gate and a floating gate is formed by using the first poly-silicon as a material of a floating gate, forming a material of an intermediate insulating film on this material, forming a material of a control gate on this material, and etching these materials.
As a third process, an impurity diffusing region, which includes source and drain regions of a memory element, is formed in the silicon substrate.